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  • DESIGN OF COST-EFFICIENT INTERCONNECT PROCESSING UNITS
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    DESIGN OF COST-EFFICIENT INTERCONNECT PROCESSING UNITS
    MARCELLO COPPOLA / MILTOS D. GRAMMATIKAKIS / RICCARDO LOCATELLI / GIUSEPPE MARUCCIA / LORENZO PIERALISI
    Streamlined Design Solutions Specifically for NoC To solve critical network-on-chip (NoC) architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require...

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